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| K6F4008U2E Family Document Title CMOS SRAM 512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History 0.0 1.0 Initial Draft Finalize Draft Date October 25, 2000 March 12, 2001 Remark Preliminary Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. -1- Revision 1.0 March 2001 K6F4008U2E Family FEATURES * * * * * * CMOS SRAM GENERAL DESCRIPTION The K6F4008U2E families are fabricated by SAMSUNGs advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. 512K x 8 bit Super Low Power and Low Voltage Full CMOS Static RAM Process Technology: Full CMOS Organization: 512K x8 bit Power Supply Voltage: 2.7~3.3V Low Data Retention Voltage: 1.5V(Min) Three State Outputs Package Type: 48(36)-TBGA-6.00x7.00 PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1, Typ.) 1.0A2) Operating (ICC1, Max) 2mA PKG Type K6F4008U2E-F Industrial(-40~85C) 2.7~3.3V 551)/70ns 48(36)-TBGA-6.00x7.00 1. The parameter is measured with 30pF test load. 2. Typical value are at VCC=3.0V, TA=25C and not 100% tested. PIN DESCRIPTION 1 2 3 4 5 6 FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. A A0 I/O5 I/O6 VSS A1 A2 CS2 WE DNU A3 A4 A5 A6 A7 A8 I/O1 I/O2 VCC Row select B C Row Address Memory Cell Array D 48(36)-TBGA E VCC I/O7 I/O8 A9 OE A10 A18 CS1 A11 A17 A16 A12 A15 A13 VSS I/O1 F I/O3 I/O4 A14 I/O8 Data cont I/O Circuit Column select G Data cont Column Address H Name Function Name Function CS1 CS2 WE OE CS1, CS2 Chip Select Inputs OE WE A0~A18 Output Enable Input Write Enable Input Address Inputs I/O1~I/O8 Data Inputs/Outputs Vcc Vss DNU Power Ground Do Not Use Control logic SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -2Revision 1.0 March 2001 K6F4008U2E Family PRODUCT LIST Industrial Temperature Products(-40~85C) Part Name K6F4008U2E-EF55 K6F4008U2E-EF70 Function CMOS SRAM 48(36)-TBGA, 55ns, 3.0V 48(36)-TBGA, 70ns, 3.0V FUNCTIONAL DESCRIPTION CS1 H X 1) CS2 X1) L H H H OE X1) X 1) WE X1) X 1) I/O High-Z High-Z High-Z Dout Din Mode Deselected Deselected Output Disabled Read Write Power Standby Standby Active Active Active L L L H L X1) H H L 1. X means dont care (Must be in low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Ratings -0.5 to VCC+0.3V(Max. 3.6V) -0.3 to 3.6 1.0 -65 to 150 -40 to 85 Unit V V W C C 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. -3- Revision 1.0 March 2001 K6F4008U2E Family RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage Ground Input high voltage Input low voltage Note: 1. TA=-40 to 85C, otherwise specified. 2. Overshoot: Vcc+2.0V in case of pulse width 20ns. 3. Undershoot: -2.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. CMOS SRAM Symbol Vcc Vss VIH VIL Min 2.7 0 2.2 -0.3 3) Typ 3.0 0 - Max 3.3 0 Vcc+0.3 0.6 2) Unit V V V V CAPACITANCE1) (f=1MHz, TA=25C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested. Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Symbol Test Conditions VIN=Vss to Vcc CS1=VIH, CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc Cycle time=1s, 100%duty, IIO=0mA, CS10.2V, CS2Vcc-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, VIN=VIL or VIH IOL = 2.1mA IOH = -1.0mA CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or 0VCS20.2V(CS2 controlled), Other inputs=0~Vcc 70ns 55ns Min -1 -1 2.4 - Typ1) 1 Max 1 1 2 15 20 0.4 12 Unit A A mA mA V V A ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current (CMOS) VOL VOH ISB1 1. Typical value are measured at VCC=3.0V, TA=25C, and not 100% tested. -4- Revision 1.0 March 2001 K6F4008U2E Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See right): CL= 100pF+1TTL CL=30pF+1TTL CMOS SRAM VTM3) R12) CL1) R22) 1. Including scope and jig capacitance 2. R1=3070, R2=3150 3. VTM =2.8V AC CHARACTERISTICS(Vcc=2.7~3.3V, Industrial product:TA=-40 to 85C) Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Read Chip Select to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 55 10 5 0 0 10 55 45 0 45 40 0 0 25 0 5 55ns Max 55 55 25 20 20 20 Min 70 10 5 0 0 10 70 60 0 60 50 0 0 30 0 5 70ns Max 70 70 35 25 25 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units DATA RETENTION CHARACTERISTICS Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CS1Vcc-0.2V1) Vcc=1.5V, CS1Vcc-0.2V , VIN0V See data retention waveform 1) Min 1.5 0 tRC Typ 0.5 2) Max 3.3 3 - Unit V A ns 1. CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) or 0CS20.2V(CS2 controlled). 2. Typical value are measured at TA=25C and not 100% tested. -5- Revision 1.0 March 2001 K6F4008U2E Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH) tRC Address tOH Data Out Previous Data Valid tAA CMOS SRAM Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE tOH OE tOLZ tLZ Data Valid tOHZ Data out NOTES (READ CYCLE) High-Z 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. -6- Revision 1.0 March 2001 K6F4008U2E Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4) CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) CS1 tAW CS2 tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4) Data out High-Z High-Z -7- Revision 1.0 March 2001 K6F4008U2E Family TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) tWC Address tAS(3) CS1 tAW CS2 tCW(2) tWP(1) tDW Data in Data Valid tDH tCW(2) tWR(4) CMOS SRAM WE Data out NOTES (WRITE CYCLE) High-Z High-Z 1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high tWR2 applied in case a write ends as CS2 going to low. DATA RETENTION WAVE FORM CS1 controlled VCC 2.7V tSDR Data Retention Mode tRDR 2.2V VDR CS1VCC - 0.2V CS1 GND CS2 controlled VCC 2.7V CS2 tSDR Data Retention Mode tRDR VDR 0.4V GND CS20.2V -8- Revision 1.0 March 2001 K6F4008U2E Family PACKAGE DIMENSIONS 48(36) TAPE BALL GRID ARRAY(0.75mm ball pitch) Top View Bottom View B B B1 CMOS SRAM Units: millimeters A1 INDEX MARK 0.65 0.65 6 A #A1 B C D 5 4 3 2 1 C1 E C1/2 F G H B/2 Detail A A 0.35/Typ. Y 0.55/Typ. Notes. 1. Bump counts: 48(8 row x 6 column) 2. Bump pitch: (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are +/-0.050 unless otherwise specified. 4. Typ: Typical 5. Y is coplanarity: 0.08(Max) -9- Side View D C Min A B B1 C C1 D E E1 E2 Y 5.90 6.90 0.40 0.80 0.30 - Typ 0.75 6.00 3.75 7.00 5.25 0.45 0.90 0.55 0.35 - Max 6.10 7.10 0.50 1.00 0.40 0.08 C Revision 1.0 March 2001 C E2 E1 E |
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